The present invention relates generally to semiconductor devices, and more particularly to III-V nanowire FETs with a compositionally-graded channel shell around a wide-bandgap core and methods of their fabrication.
The fabrication of semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by adding various dopants into portions of a semiconductor substrate to achieve specific electrical properties. Semiconductor devices include transistors, diodes, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.
Field-effect transistors (FETs) are a commonly used semiconductor device. Generally, a FET has three terminals, i.e., a gate structure or gate stack to control the charge in a channel region, a source region, and a drain region. The gate stack is a structure used to control output current, i.e., flow of carriers in the channel portion of an FET, through electrical fields. The channel portion of the substrate is the region between the source region and the drain region of a semiconductor device that becomes conductive when certain voltage is applied to the gate. The source region is a doped region in the semiconductor device from which majority carriers are flowing into the channel portion. The drain region is a doped region in the semiconductor device located at the end of the channel portion, in which carriers are flowing into from the source region via the channel portion and out of the semiconductor device through the drain region.
In nanowire FETs with uniform channel material, the charge centroid and the maximum leaking point in the sub-threshold regime is the center of the nanowire. In materials with substantial conduction band offset, if the center region or core of the nanowire has a wider bandgap material, and/or the nanowire channel has compositional grading, then the charge of the centroid and the maximum leakage point will move to the outer channel region and become closer to the gate. This often leads to improved gate control over the nanowire channel in the sub-threshold regime and better control of short-channel effects. The use of wider bandgap material in the inner region of the nanowire also often reduces off-state leakage due to tunneling (i.e., direct source-to-drain tunneling and band-to-band tunneling). However, some nanowire FETs material systems have a conduction band offset that is zero, or close to zero, making it difficult to improve gate control and short-channel effects.